1. Technical Field
The present application relates to semiconductor technology, and more particularly to Metal Oxide Semiconductor (MOS) devices and methods of making MOS devices.
2. Related Art
MOS devices such as transistors and similarly structured memory cells are known that have a configuration as shown in FIG. 1. The MOS device shown in FIG. 1 is an N-type MOS device, referred to as an NMOS device 100. The NMOS device 100 is formed on a semiconductor substrate 102, such as a silicon wafer. A P-well 104 is formed in the substrate 102, which will serve as body and active region for the NMOS device 100. The P-well 104 can be formed, for example, by known well implantation processes, such as the implantation of boron (B) ions, which introduces P-type impurities. The NMOS device 100 also includes diffusion regions 106 and 108, which can serve as the source and drain, respectively. The NMOS device 100 includes a gate structure, which includes a gate oxide layer 110 and a polysilicon gate electrode 112. The gate oxide layer 110 is typically formed by performing a thermal oxidation process on the upper surface of the substrate 102, followed by a deposition process for depositing polysilicon for the gate electrode 112. The gate oxide layer 110 and gate electrode 112 can then be formed by patterning the oxide and polysilicon layers, for example using a photolithography process. In some cases, the gate structure can be formed prior to the formation of the diffusion regions 106 and 108 so that the gate can be used to assist with alignment of the diffusion regions 106 and 108.
Next, an interlevel dielectric (ILD) structure 116 is formed for electrically isolating various structures of the NMOS device 100. Known back-end-of-line (BEOL) processes are performed, which will include fabrication of vias and conductive lines including the source interconnect line 118, drain interconnect line 120, and gate interconnect line 122.
For devices such as the NMOS device 100, simultaneous high voltage and low voltage limitations are often imposed for design objectives. These simultaneous objectives are often contradictory. For example, high voltage transistors with high junction breakdown characteristics and high punch-through characteristics are desirable for passing a relatively high voltage. However, in order to efficiently pass the high voltage from drain to source without significant voltage drop, the transistor preferrably should also have low channel resistance. These contradictory high voltage requirements can sometimes be met using long channel length transistors. However, as the technology is scaled down, shorter channels are desired, increasing the difficulty of integrating high voltage transistors such as the device 100 that have suitable on-resistance and breakdown voltage levels.